1. Technical Field
Embodiments of the present invention generally relate to computer networking architectures. More particularly, embodiments of the invention relate to a network interface between a processor internal bus and an external bus that enables enhanced networking performance.
2. Discussion
In the highly competitive computer industry, the trend toward faster processing and increased functionality is well documented. While this trend is desirable to the consumer, it presents a number of challenges to computer designs as well as manufacturers. One concern relates to networking architectures, particularly in view of the rapidly increasing popularity of the Internet in modern society. A typical networking architecture for a system-on-chip is shown in FIG. 1 at 10. It can generally be seen that a networking processor 12 is coupled to an internal bus 14 and typically has an internal memory 18. The memory 18 may be either on-chip or off-chip, and is also coupled to the internal bus 14, where the processor 12, memory 18 and internal bus 14 may be part of a “system-on-chip” (SOC). It can further be seen that the SOC also includes an external interface engine (EIE) 20 coupled to the internal bus 14 and an external bus 22. The external bus 22 supports a bus protocol such as the peripheral component interconnect (PCI version 2.2, PCI Special Interest Group) protocol, the universal test and operation physical interface for asynchronous transfer mode (Utopia Level 1/2/3, ATM Forum Technical Committee) protocol, and/or others as needed. Thus, the EIE 20 communicates over the external bus 22 in accordance with the applicable protocol, stores network data to memory 18 for use by the processor 12, and retrieves network data from memory 18 in order to implement various networking functions.
While the above-described architecture 10 has been satisfactory in certain networking environments, significant room for improvement remains. For example, the conventional EIE 20 operates as a single engine that is only capable of communicating in accordance with one external bus protocol. Thus, if it is desired to utilize multiple protocols, additional EIEs are necessary. Furthermore, if EIEs are added it is difficult to share physical resources across multiple logical queues according to user-determined priorities. This difficulty in assigning resources to the protocols results from the fact that there is no mapping of logical queues onto the multiple protocol interfaces.
In addition, various protocols often use different data ordering and arrangements. For example, some protocols may require a technique commonly referred to as endian-swapping in order to insure that the network data has the same “look and feel” regardless of the external bus protocol. It should also be noted that as bus protocols transition from one generation to the next, such as going from Utopia Level 2 to Utopia Level 3, it may be desirable to add interfaces to support the upgrade. In the conventional architecture 10, however, adding new interfaces can be difficult, and often alters the internal look and feel of the network data. Furthermore, such modifications can complicate processing.
It will be further be appreciated that the EIE 20 typically has no memory region and therefore lacks the ability to buffer the network data between the internal bus 14 and the external bus 22. This can be undesirable with regard to networking performance for a number of reasons. For example, internal data transport is not isolated from network transients resulting from network bursts and dry spells. In this regard, processing speed is usually equal to the average data arrival rate. Typically, the maximum rate on a line is significantly higher than the average arrival rate. Indeed, certain network processors 12 are designed to pass about 40 megabytes of information per second, whereas data throughput on the external bus 22 can reach speeds as high as 100 megabytes per second. Thus, internal transport latencies are not decoupled from external transport latencies, and the lack of an overflow capability can result in packets being dropped during network bursts.
It is important to note that the typical EIE 20 uses a read-write data transport scheme wherein data is written to the memory 18, and the processor 12 accesses the off-chip memory 18 via a read operation over internal bus 14. Read operations are more costly from a latency standpoint than write operations because the requestor of the data must often wait a number of cycles for the data to be returned. Furthermore, the number of cycles usually cannot be predicted with precision. As a result, efficiency may suffer. Furthermore, the EIE 20 is traditionally unable to provide for service prioritization, classification of traffic and amortization of data transport costs. As a result, more of the processing time available to processor 12 must be spent managing the network data and less time can be spent processing the actual packets in the network data.